1. Field of the Invention
This invention relates in general to an analog-to-digital (A/D) converter and, in particular, to an A/D converter requiring no timing signal for synchronously-triggered conversion operation. More particularly, this invention relates to an A/D converter that converts analog signals into digital in a limited number of rippling feedback operations in short time delay periods utilizing simple circuit configuration.
2. Description of Related Art
Conventional A/D converters employ one of three methods to perform the analog-to-digital conversion of signal. A slow A/D converter based on a first A/D conversion method employs a digital counter that is used to count through a range of guess values, which are converted by a digital-to-analog converter for comparison with the input analog signal. The digitally-converted data with the closest comparison result is obtained as the conversion result. A relatively higher-speed A/D converter based on a second A/D conversion method employs a multiple of 2.sup.n comparators to implement its conversion. The voltage of the input analog signal is divided into 2.sup.n divisions that may have their voltage determined. An encoder is then employed to obtain the digitally-converted result based on the determined voltage. Another high-speed A/D converter based on a third A/D conversion method employs a logical scheme to set the data code, which, after its D/A conversion, is then compared with the input analog data, with the comparison result fed back to the logic circuitry for modification of the data code for output as the converted A/D result.
FIG. 1 is a schematic diagram showing the circuitry of a conventional low-speed A/D converter. For example, assume an up-counter 12 is preset to an initial value of 0. The counter value present at the Q outputs of the up-counter 12 is relayed to the D/A converter 11 which is then converted into analog data and compared with the analog input V.sub.in in the comparator 10. The result of comparison at the comparator 10 is sent to the two-input AND gate 13 for determining whether or not the up-counter 12 should cease its counting. This is determined by the AND gate 13, which allows the counter 12 to be triggered for one up-count when the clock signal Clk is ANDed with a logical zero output signal from the comparator 10. In other words, when the comparator 10 has a logical one output signal, which reflects the fact that both the comparator inputs are found equal, the AND gate 13 no longer relays the up-counting clock signal Clk to trigger the counter 12 for further up-counting. At this instance, the Q outputs of the up-counter 12 are the digital equivalent of the input analog signal V.sub.in. The clear input Clear allows the counter 12 to reset for initiation of another A/D conversion cycle. The A/D converter based on the circuitry of FIG. 1 is characterized by its slow speed in obtaining its conversion result. Up to 2.sup.n clock cycles may be required to conclude one conversion operation.
The circuitry of FIG. 2 depicts another conventional converter for A/D conversion that operates at relatively higher speed. In comparison with the circuitry of FIG. 1, this is substantially a comparator-based A/D converter circuitry based on a series of discrete converters 20 arranged in a parallel network. The input signal V.sub.in is input to all the positive input terminals of the eight comparators 20, while a maximum input comparator signal supplied by a reference source is divided among a series train of eight resistors R1, R2, . . . , and R8, with each division successively input to the negative input terminal of the eight corresponding comparators 20. Each of the eight comparators then performs its compare operation and relays its compared result to the corresponding one of the eight inputs of a priority encoder 21. Based on the inputs, the priority encoder 21 produces an output at its Q terminals representing the specific one of the eight comparators that delivers a matched comparison result. In this depicted example, three Q output bits Q.sub.2, Q.sub.1 and Q.sub.0 are required to represent the eight input bits 0, 1, . . . , 7. In case there are more than one matched input among the eight, the encoder 21 is designed to select the one that has an assigned higher priority as the determined output. This circuitry, although able to perform much faster than the circuitry of FIG. 1, requires more independent comparators to operate. In general, a total of 2.sup.n comparators will be required for a resolution of n bits in the converted result. In the depicted example, a total of eight compared to one in the circuitry of FIG. 1 are required. When there is a requirement for higher resolution, increased circuitry complexity becomes necessary, and the cost increases as a result.
FIG. 3 is schematic diagram of another conventional high-speed A/D converter employing a controlling logic circuitry 32, which generates an initial value that is relayed to the D/A converter 31 via a switch unit 33. The D/A converter 31 converts the digital value produced by the controlling logic circuitry 32 into an analog signal that is then relayed to a comparator 30 for comparison with the input analog signal V.sub.in. The comparator sends its compared result back to the controlling logic circuitry 32, which then adjusts its generated value for another cycle of comparison, until a match is finally reached. Two primary time delays arise in this system. One is that required for the processing time in the controlling logic circuit 32, and the other is that required for the comparator 30 to perform its comparison. Assuming a three-bit A/D conversion, a 100 ns delay time is required for both the two primary delays. A total of 3.times.100 ns.times.2=600 ns is required. When the conversion resolution is high, the total conversion time increases proportionally.
Thus, it is apparent that these conventional A/D converters suffer the disadvantages of either slow operation time or complicated circuitry configuration, or both.